1. Field of the Invention
The present invention relates to a method of forming a pattern for a semiconductor device. More particularly, the present invention relates to a method of forming a pattern of which line width is much smaller and finer in a cell region than in a peripheral region of a semiconductor device.
2. Description of the Related Art
Forming a fine circuit on a semiconductor substrate includes an impurity implantation, a patterning process and an electrical connection between separated portions. Impurities are implanted on a small surface portion of a silicon substrate in a precise amount, and then a sacrificial layer is formed on the substrate including the impurities. Then, the sacrificial layer is patterned in accordance with a mask pattern, and the substrate or a thin layer on the substrate is partially removed using the sacrificial layer pattern as a mask, so that the substrate or the thin layer thereon has a pattern of separated portions. Finally, the separated portions of the substrate or the thin layer are electrically connected with each other, thereby forming a semiconductor device including an integrated circuit such as a very large scale integration (VLSI) chip. Here, a photolithography process, in general, is performed for defining the implantation region or forming the pattern.
According to the photolithography process, a photoresist material that is very sensitive to light is coated on the semiconductor substrate or a wafer, thereby forming a photoresist film on the wafer. The light such as an ultraviolet ray, an electron beam or an X-ray is irradiated onto the photoresist film through a mask or a reticle. Then, the photoresist film is selectively exposed to the light and developed through a predetermined process, thus finally a photoresist pattern is formed in accordance with or contrary to a mask pattern, which is referred to as a positive pattern or a negative pattern. In a subsequent process, while a portion of the substrate or a thin layer thereon covered by the photoresist pattern is protected from the process, the other portion of the substrate or the thin layer thereon exposed through the photoresist pattern is subjected to the process.
When the photoresist pattern is used as an etching mask, a portion of the thin layer exposed through the photoresist pattern is partially etched away, thus the thin layer on the substrate is formed into a predetermined pattern in accordance with the photoresist pattern.
The above photolithography process has certain drawbacks. Firstly, when the photoresist film is exposed to the light, an exposure condition may be minutely different from each point in a shot, so that a line width is varied throughout chips on the wafer.
Secondly, when the photoresist film is exposed to the light, an exposure condition of every shot may be minutely different from each other, so that a critical dimension (CD) of the chip is varied in accordance with a region of the wafer.
Thirdly, when an etching process is performed using the photoresist pattern as a mask, an edge line of an etched portion of the thin layer becomes very rough since the photoresist pattern becomes non-uniform, which is referred to as a line edge roughness phenomenon.
Due to the above-mentioned problems, a line width distribution of the patterns in each unit cell in a chip has a substantial effect on performance of the highly-integrated memory device such as the VLSI chip. Non-uniformity of the line width distribution causes electrical characteristics of each unit device in a chip or in a wafer to be non-uniform, thus causing various process failures in the semiconductor device. In addition, a non-uniform etching of the photoresist film degrades a short channel characteristic of the device, and a gate size reduction accelerates the degradation of the short channel characteristic of the device.
Accordingly, a manufacturing process for a high-integrated semiconductor device has required a new method of forming a pattern with more accuracy and fineness than by the photolithography process.
For example, Japanese Publication Patent No. 2002-280388 discloses a method of forming a line and space pattern having a minute pitch smaller than a resolution of the exposing process. In detail, a second insulating layer is formed on a sidewall of a first insulating layer pattern, and then the first insulating layer pattern is removed. An etching process is performed using the second insulating layer as an etching mask, thereby forming a pattern. However, when the second insulating layer is used as an etching mask, the pattern has the same line width across a whole surface of a substrate, and as a result, the pattern may not have a line width greater than that of the second insulating layer at any local area on the substrate. In addition, since the second insulating layer is shaped in accordance with the shape of the sidewall of the first insulating layer, various patterns may not be formed when the second insulating layer is used as an etching mask.